Issue link: https://resources.pcb.cadence.com/i/1310896
www.cadence.com 2 Sigrity SystemSI Signal Integrity Solutions simulates end-to-end channel behavior to produce comprehensive eye diagrams and bathtub curves and to predict BER performance. By identifying jitter and noise impacts, you can quickly make design improvements. The tool fully supports industry-standard IBIS AMI TX and RX models in simulations that assess the effectiveness of chip-level signal conditioning along with clock and data recovery. Enhanced design flow Sigrity SystemSI technology includes an easily used block-based topology editor to rapidly capture a single net or a complete multi-board bus. With a wizard and basic templates, you can start your design process early, and swap in progressively refined models as your design takes shape. To maximize accuracy, you can use detailed S-parameter models, generated from tools such as Cadence Sigrity PowerSI ® technology. The Cadence open Model Connection Protocol (MCP) simplifies and automates the hook-up, so you can avoid tedious and error-prone model connection tasks. Compliance kits and graphic- and text-based outputs help you quickly identify potential risks. Maximum accuracy Assuming an ideal power delivery network (PDN) is extremely dangerous for high-speed designs. Noise is easily propagated in boards and packages due to the low-loss nature of the substrate materials used. In designs that approach multi-gigabit operating speeds, eye quality can be significantly impacted by the presence of even small noise currents in the PDN. Sigrity tools extract signals coupled with the associated PDN, enabling simula- tions that account for these real-time interactions. This is essential because the impact of PDN noise can rival and even surpass traditional signal-to-noise crosstalk. The ability to utilize structurally correct SPICE subcircuits for the I/O circuit models enables the Sigrity SystemSI tool to include these effects that are typically masked in other tools. Supported Interfaces • Available for use with Windows and Linux • Models: SPICE (HSPICE and others), IBIS (native IBIS, BIRD95/98, AMI), S-parameters (Touchstone/Cadence Sigrity Broadband Network Parameter (BNP) syntax), Cadence Sigrity MCP • Parallel bus interface compliance checks included for DDR2, DDR3, DDR4, LPDDR3, LPDDR4 • Serial Link compliance checks included for PCI Express ® (PCIe ® ) 3.0, PCIe 4.0, SFP+, 10GBASE-KR, HDMI, USB 3.0, USB 3.1, 100BASE-T1 Cadence Services and Support • Cadence application engineers can answer your technical questions by telephone, email, or Internet—they can also provide technical assistance and custom training Figure2: PCIe Gen3 SerDes simulation incorporating IBIS AMI models and accounting for back-channel simulations Figure 3: Eye contours showing the impacts of power noise