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www.cadence.com 3 Cadence Schematic Capture can generate BOMs using up-to-date, comprehensive, and complete infor- mation, and create reports through the Crystal report engine. Architecture/database integration • Accepts plug-ins for programmable logic design and analog simulation • Allows for design creation and simulation in the same environment • Works with Microsoft's ODBC-compliant databases • Users can access data directly in an MRP, ERP, and PDM system Documentation Cadence technology provides an extensive set of documentation, which includes user guides, context-sensitive help (F1), reference guides, online tutorials, and multimedia demonstrations. The documentation set helps you to: • Find the answer you need by searching the online help system and navigate quickly between related topics with extensive hypertext cross-references • Learn the technology with the help of online interactive tutorials • Find information on error and warning scenarios FPGA Allegro Design Entry CIS, together with Allegro FPGA System Planner, addresses the challenges that engineers encounter when designing large pin-count FPGAs on the PCB board—which includes creating the initial pin assignment, integrating with the schematic, and ensuring that the device is routable on the board. They deliver a complete, scalable technology for FPGA-PCB design-in and co-design that automates creation of optimum "device-rules-accurate" pin assignment, symbol creation, and flow. By replacing manual, error-prone processes with automatic pin assignment synthesis, this unique placement-aware solution elimi- nates unnecessary physical design itera- tions while shortening the time required to create optimum pin assignment. Design-in Allegro Design Entry CIS supports the FPGA design flow with the ability to quickly import and/or create FPGA symbols and components. With an ever- increasing pin count and complexity for FPGA parts, the easy-to-use GUI-based options of Design Entry CIS can be used to create single and multi-section FPGA parts based on the device I/O pin files. Support for split parts, power pin visibility, pin shape, and pin group management provide flexibility to tailor symbol creation to the design needs. FPGA components can also be exported using the export FPGA dialog box. The export FPGA function completes the bi-directional link between FPGA designers and PCB designers. Co-design Allegro FPGA System Planner provides a complete, scalable solution for FPGA-PCB co-design that allows users to create an optimum correct-by-construction pin assignment. FPGA pin assignment is synthesized automatically based on user-specified, interface-based connec- tivity (design intent), as well as FPGA pin assignment rules (FPGA rules), and actual placement of FPGAs on PCB (relative placement). With automatic pin assignment synthesis, users avoid manual error-prone processes while shortening the time to create initial pin assignment that accounts for FPGA placement on the PCB (placement-aware pin assignment synthesis). This unique placement-aware pin assignment approach eliminates unnecessary physical design iterations that are inherent in manual approaches. Allegro FPGA System Planner is integrated with both Design Entry CIS and Allegro PCB Editor. It reads and creates schematics and symbols. In addition, a floorplan view uses existing footprint libraries from Allegro PCB Editor. Should placement change during layout, pin optimization using FPGA System Planner can be accessed directly from Allegro PCB Editor. Specifications System requirements • Pentium 4 (32-bit) equivalent or faster • Windows XP Professional, Vista Enterprise • Minimum 512MB (1G or more recommended for XP and Vista Enterprise requirements) • 300MB swap space (or more) • DVD-ROM drive • 65,000 color Windows display with minimum 1024 x 768 (1280 x 1024 recommended) Figure 2: Visibility into complete part information ensures informed part selection, reducing the risk of delays later in the design process CIS Explorer

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