OrCAD datasheets

www.cadence.com 4 Allegro PCB Design Solution successful interconnect solution far faster and more easily than ever before, reduc- ing design cycle time through increased efficiency and productivity. (See Figure 5.) Getting routes out of dense BGAs is increasingly difficult for PCB designers. With increasing pin counts and shrink- ing pin pitches, the time PCB designers spend on getting routes in and out of BGAs has gone up significantly. The tradi- tional approach of performing breakouts first then routing the traces between two BGAs is running out of steam because resolving the resulting crossovers takes up a lot of time and board real estate. AiBT Auto-interactive Breakout Technology (AiBT) improves user efficiency by allowing users to plan to break out on both ends. AiBT can be used with the new, Split View, and Bundle Sequence commands to dramatically shorten the time required to develop a high-quality and properly ordered breakout solution (see Figure 6). High-Speed Option Increasing use of standards-based advanced interfaces such as DDR3, DDR4, PCIe, USB 3.0 are bringing a set of constraints that must be adhered to while implementing a PCB. The Allegro PCB Designer High-Speed Option makes adhering to constraints on advanced interfaces quick and easy. It offers an extensive range of electrical rules to ensure that the PCB design imple- mentation is complaint with the specifica- tion for advanced interfaces. Additionally, it allows users to extend the rules through the use of formulas with existing rules or post-route data such as actual trace lengths. The High-Speed Option allows users to apply a topology to a set of signals. A topology can include a set of routing preferences as well as constraints such as putting the termination resistor closer to either the driver or a receiver on a signal. The constraint-driven PCB design system then provides feedback through the constraint manager if a signal doesn't conform to the topology or the rules asso- ciated with the topology, ensuring that issues are identified (and therefore can be addressed) as quickly as possible. The High-Speed Option also enables checking of delays through vias, connec- tor pins, and IC package-pin for die2die length/delay matching. It includes, utilities to identify trace segments crossing voids (return path issues that cause re-spins), supports back drilling (remove through hole antennas) as well as provides a timing environment that can acceler- ate timing closure of critical nets up to 60-70%. Accelerated Timing Closure As the data rates increase and supply volt- ages decrease in today's advanced inter- faces like DDR3/DDR4, PCIe, SATA, etc., PCB designers must spend more time to ensure signals in an interface meet timing requirements. With increasing density on PCBs, the effort to get to timing closure— ensuring all signals meet timing require- ments—can increase significantly. PCB designers need new tools to meet this increasingly complex challenge. Timing Vision Timing Vision is an innovative and unique environment that allows users to graphi- cally see real-time delay and phase infor- Figure 6: Split View allows working on both ends of a zoomed-in interface Figure 5: The Design Planning Option allows users reduce layer counts and shorten design cycle through design planning

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