Issue link: https://resources.pcb.cadence.com/i/1180526
PSpice User Guide October 2019 871 Product Version 17.4-2019 © 1999-2019 All Rights Reserved. D data collection, limiting 710 data collection, limiting file size 710 DC analyses displaying simulation results 99 see also DC sweep analysis, bias point detail analysis, small-signal DC transfer analysis, DC sensitivity analysis DC sensitivity analysis 418, 487 introduction 36 DC stimulus property 477 DC sweep analysis 418, 472 to 480 about 473 curve families 479 example 97 introduction 36 nested 477 setting up 97 stimulus 476 DELAY stimulus property (digital) 616 derivative problems 838 design preparing for simulation 43, 136 Design Entry HDL library structure 61 to 67 local (design) libraries 65 reference libraries 63 simulate a design from within 95 views 65, ?? to 66 Design Templates 91 DESIGN_NAME.MAP 48 DESIGN_NAME.NET 47 DESIGN_NAME-ROOT_SCHEMATIC_NA ME.NET 47 DESIGN_NAME-ROOT_SCHEMATIC_NA ME-PROFILE_NAME.SIM.CIR 47 device noise 502, 505 Device types characteristic curves-based 208 template-based 211 device types breakout parts 153 E and G devices 355 Model Editor 208, 211 passive parts 152 PSpice-equivalent parts 354 three- and four-terminal 428 devices, see parts or models diagnostic problems 839 dialog box Advanced Analog Options 433 Arguments for Measurement Evaluation 781 Display Control (Probe) 693 Display Measurement Evaluation 785 Measurements 780 Simulation Message Summary 753 Traces for Measurement Arguments 782 DIG_GND stimulus property (digital) 617 DIG_PWR stimulus property (digital) 617 DIGDRVF (strengths) 398 DIGDRVZ (strengths) 398 DIGERRDEFAULT (simulation option) 636 DIGERRLIMIT (simulation option) 636 DIGIOLVL (simulation option) 385 digital device modeling 375 to 412 digital primitives list ?? to 381 digital primitives syntax 382 to ?? example "U" device declaration 385 functional behavior 377 inertial delay 391 input/output characteristics 393 to 403 AtoD and DtoA subcircuits 400 charge storage on nets 399 configuring the strength scale 397 controlling overdrive 398 defining output strengths 396 I/O model 393 I/O model parameters 395 internal delay functions 390 overview 376 propagation delay calculation 390 timing characteristics 387 to 392 timing model 387 unspecified propagation delays unspecified timing constraints 389 transport delay 392 digital primitives see also parts input (N device) 400 output (O device) 400 propagation delays, see timing model syntax 382 timing model, see timing model digital signals, see traces digital simulation ?? to 637 adding digital trace expressions 627