Cadence PCB Best Practices

Constraint Compiler User Guide

Issue link: https://resources.pcb.cadence.com/i/1180274

Contents of this Issue

Navigation

Page 22 of 25

Allegro Constraint Compiler User Guide Allegro Constraint Compiler October 2019 25 Product Version 17.4-2019 © 1999-2019 All Rights Reserved. Compiler Results ■ Generates Match Group HS-PORT_DATA with the pin-pairs between U20 and U21 for Net Class HS-PORT_DATA with the following rules: ❑ Relative Propagation Delay Tolerance = 50 ❑ Max Propagation Delay = 2500 ■ Generates match group HS-PORT_ADDR with the pin-pairs between U20 and U21 for Net Class HS-PORT_ADDR with the following rules: ❑ Relative Propagation Delay Tolerance = 100 ❑ Max Propagation Delay = 4000 ■ Relative propagation delay with an empty Delta field matches all match group members within the Tolerance ❑ Setting the Delta field to 0 to match all match group members to the longest pin to pin manhattan length within the defined Tolerance (+/- Tolerance) ❑ Setting the Delta to anything other than 0, on a specific net, gets treated as a +/- offset to the member which yields the longest pin to pin manhattan length within the Tolerance ■ Propagation delay keeps the pin-pair connection below the Max length ■ When imported into Constraint Manager, match group name have prefix MG_ and based on the Net Class name Object Rule Table (Class to Class Rules) The Object Rule Specification table can also be used to create Class to Class relationships between type classifications defined in an Object table. Objects grouped under a type classification are processed and generate the required spacing Net Classes to support the Class to Class spacing requirements. Each type-to-type relationship reference to either a rule specification, rule set or an existing spacing CSet (Spacing Set:) to apply an appropriate rule.

Articles in this issue

view archives of Cadence PCB Best Practices - Constraint Compiler User Guide