XNet Creation and SI Simulation in Allegro System Capture
Learn more at Cadence Online Support - http://support.cadence.com
© 2019 Cadence Design Systems, Inc. All rights reserved w orldw ide. Page 4
Overview
This document explains what are XNets and how they are created in Allegro System
Capture. It also explains how to configure and perform an SI Simulation from within
Allegro System Capture.
XNets
A net is an electrical connection from one pin to another pin, or pins, on the same
device, or on a different device.
If the path of a net traverses a passive or discrete device, such as a resistor, inductor,
or capacitor, then each net segment is represented by an individual net entity. The
constraint system interprets these net segments as a contiguous eXtended Net, or
XNet. An XNet can also traverse connectors and cables in a multi-board configuration.
To better understand what is an XNet, take a look at the following example.
There is a connection between pin B of the device on the left with pin DN of the device
on the right. The two nets along with the discrete is considered one XNet.
Older design-capture applications require a DML model to be defined on the discrete
device for creating an XNet across the device. This forced an additional step of
assigning a model.
In contrast, Allegro System Capture does not require DML models for creating XNets.
This is called the DML-independent mode for XNet creation.
