Allegro System Capture App Notes

Allegro System Capture Features

Issue link: https://resources.pcb.cadence.com/i/1180230

Contents of this Issue

Navigation

Page 18 of 82

19 © 2019 Cadence Design Systems, Inc. Cadence confidential. • In case width of bus coming from a hierarchical block is reduced, unused bus bits coming from block can be purged Purge Unused Bus Bits

Articles in this issue

view archives of Allegro System Capture App Notes - Allegro System Capture Features