Allegro Integrated Analysis and Checking – IR Drop Workflow: RAK
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Purpose
This RAK demonstrates the IR drop workflow of Allegro Integrated Analysis and
Checking that is used to analyze power integrity issues. This document captures the
step-by-step instructions on loading a PowerTree file to do the basic IR drop set up,
running IR drop analysis, and using IR drop Table and Vision effectively.
Audience
This document is intended for hardware engineers and Allegro PCB Designer users
who wish to analyze their designs for IR drop issues and utilizing the Allegro Sigrity SI
analysis workflows.
Directory Structure
Download the following files, available under the attachment section, to run the lab
exercise:
◼ IRDrop.brd – Board layout file
◼ PCIe_DualDimm.pwt – PowerTree file
Overview
IR drop analysis is the Power Integrity (PI) simulation workflow and is used to identify
potential voltage drop issues in the interconnect that makes up the power delivery
network. The set up required to run the analysis is based on the PowerTree technology.
You need to load PowerTree to provide a set of DC nets for analysis and all necessary
set up details.
