Allegro System Capture: Caching and Part Management
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Purpose
This RAK is one in a series introducing the set of features provided in Allegro System
Capture, an application that enables designers to capture a PCB design in schematic
form and add constraints to the design.
Overview
This RAK is designed to provide you with step-by-step guidance on how to create a
schematic design using Allegro System Capture. The schematic design is passed to the
layout tool, Allegro PCB Editor, to place and route the board-level design. Any changes
made in the layout are then brought back to the schematic to complete the round trip.
This RAK is one in a series on schematic capture in System Capture:
▪ Overview of Schematic Capture
▪ Constraining High Speed Designs from the Schematic
▪ Creating and Reusing Hierarchical Designs
▪ Navigating and Documenting your Schematic
▪ Creating Variants and BOM Reports
▪ Importing Design Data
▪ Caching and Part Management
In this RAK, you'll learn about component caching features and part management.
Download
RAK testcase database, Scripts and References can be found at 'Attachments' and
'Related Solutions' sections below the PDF.
This RAK pdf can be searched with the document 'Title' on https://support.cadence.com
