# Notes on Impedance - Part 2

April 19, 2018

If one is good, then two should be even better. That's not really the principle behind differential pairs, but it's a place to start. Each line has resistance/impedance, so two of them would have half, right? Well yeah, all things being equal, two resistors in parallel cut the resistance while two in series double it up.

But when it comes to diff-pairs, they're not equal; they're opposite. It's tempting to think when we see P and N (or M) in the net names that the P is the signal, and the N is the ground return path, but that's not so.

Image credit: ETAG -note the geometries involved for outer and inner layer edge-coupled lines.

There are three different values in play: the positive, the negative, and the neutral ground. If we're doing it right, the ground isn't returning anything. It's there to achieve the correct impedance and shield the P and N lines.

Here's the one weird trick that the pair do: if you look at the output of a differential amplifier, the two signals are a mirror image. The mirror line is the reference point where the receiver reads the signal. If the sum of the P and N is below the common line, then you have a logical low. When the sum goes higher, you flip the bit to a one.

This fine line between a binary zero and one is unique in that it doesn't take much voltage to make the change in logic, which is essential when you're on battery power. Since the pair sees the same or nearly the same interferences along the way, those effects get factored out when we measure the difference between the two lines at the far end.

Said another way, a few millivolts of noise coupled onto the two lines will drive the positive higher and the negative lower so the noise–from whatever source–will be canceled out of the comparison. That's what the nerds call "common mode." The common mode voltage gathers common mode noise simply because every piece of copper is an antenna. Common mode rejection is the coin of the realm. It's up to the comparator at the other end of the line to sort out the two messages and determine if the intention is to send a one or a zero. And then do it again and again and keep doing it so that you can see (and like!) the cat video that mom uploaded.

## Got a Match?

The thing is,the two strands of copper–whether in a cable or on the board–need to be as similar as possible so that they are not biasing the message one way or another. The faster the bits are flipping, the more precise the two lines have to be. In a robust system where the data rate is moderate, we can do all of the length matching near the driver. This is the good old static phase matching. Casual length matching works pretty well with wide busses like DDR.

Image credit: Author  -differential pairs meandering and necking down.

When the signals are going warp speed, we have to do corrections at every corner or other discontinuity. Dynamic phase matching is a real pain to route, but it's necessary so that the localized noise sources hit the waveform of both lines with the same impact. Keeping that symmetry all the way down the lines is becoming more common so if you're not doing it now, look into it. USB3 or MIPI lines are by definition more serialized, so the whole shebang goes down a few precious lines that need greater care.

Image credit EDN this shows what is going on with a group of traces in the digital realm.

## Storytime

Like Grandpa sitting on the porch, let me tell you about the days when 40 gigabytes per second meant something. The year was 2001. I remember that because I'll always remember where I was on 9/11. Those ceramic substrates weren't going to design themselves. We were passing OC768 signals off of the fiber through a pair of Gilbert connectors onto the device, ducking under the seal-ring, back up onto the surface on layer 3 and stopping just short of the die cavity. From there... Where was I? Go get your Grand Daddy some lemon-aid.

Thank you, so much.

Where was I again? Oh yeah, the edge of the cavity where the bond ribbons took over. An ordinary gold wire wasn't good enough for the 40s. We made sure the gap was narrow by insisting that the die attach machine stopped scrubbing the die back and forth when it got nearest the high-speed side. Let all those 10Gb/s lines on the other side fend for themselves on this multi-chip module. The 10 G crossed over to the other chip where they became a whole slew of 2.5s and spread out to the LGA pads. There must be something about cutting the speed into quarters that just works.

One day, Cisco came in and demonstrated how awesome 40 Gb/s could be.

"Here's every Hi-Def channel in the Bay Area streaming; all six of them.”

(Diagram comes to life).

(Needle moves a little).

“This is 1,000 people on the phone.”

(Diagram starts to show signs of stress).

(Graph gets excited and the eye diagram looks like it could use a little Visine).

But none of that's important right now. Have you seen my slippers? Oh, yes, they're right here on my feet.

Thanks again, kiddo.

Let's see. We were talking about the big 40s, right? Those babies were so tuned up, you couldn't tell them apart if you held them up to a mirror. It wasn't place and route, it was route then place! Every corner was triple faceted. Every mil (ya see, we used mils back in those days. Mils! And we liked them.) Where was I? Yeah, every mil of those traces was modeled and simulated within an... Zzzzzzzzz

You still awake? How about a little practical advice? Not all differential pairs have to be edge coupled. The image presented is normally two tracks side by side. If you don't have room for that, such as when you're escaping a big connector or IC, you can stack the two traces on adjacent layers.

Broadside coupling has another advantage in that the lines follow the same path, so there's never any phase matching. It also solves the problem of P and N crossing since you merely peel off to whichever pin the signal wants. Is it not a thing of beauty?

The disadvantage is that you take up four layers instead of three and you have to be mindful of layer-to-layer registration. Ground-Signal-Signal-Ground is a pretty common stack-up configuration anyway. Nevertheless, running from the connector to the ESD diodes in this way can solve a tricky problem.

A maxim of the internet is that you can ask a question and maybe get an answer. Write something that is incorrect, and a line will form to tell you that you are wrong. The commenting section is all yours, thankfully.

• Still craving? Here is,"The Deeper Dive"from All About Circuits
• Not done? ETAG has lots of images and words on impedance
• EDN (Electronic Design News) gets after the non-so-evil Eye Diagram

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Using TimingDesigner to Generate SDC Timing Constraints

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Notes on Impedance - Part 1

There's scarcely a printed circuit board that doesn't have some form of impedance control. The trend is mor...