Why Use SerDes?

October 6, 2020 Cadence PCB Solutions

Key Takeaways

  • Learn about SerDes functionality.

  • Gain a greater understanding of why we use SerDes.

  • Learn how the use of SerDes benefits both the design and functionality of your circuits.

 Future design for Microcontroller with embedded SerDes use

Future design for Microcontroller with embedded SerDes use.

Manufacturing, within the confines of the electronics industry, mirrors other sectors in terms of the need for cost-effectiveness in design philosophy. Invariably, design decisions depend on whether the final design requires a particular component to function and, if so, what are the most cost-effective methods of implementation.

Within the field of electronics resides the more specified area of high-speed communications. This specific field requires extreme performance and accuracy in its designs to promote reliable functionality. However, with today’s applications, the movement of high-speed data inherently includes a certain level of complexity. We typically utilize components with embedded SerDes (Serializer/Deserializer) to offset these deterrents to a device’s functionality. 

In summary, we use SerDes to mitigate some of these complexities while affording a more streamlined approach to maintaining high levels of functionality.

The Purpose of SerDes

A Serializer/Deserializer is a pair of functional blocks utilized in high-speed communications. One of the significant benefits of its use is to compensate for limited inputs and outputs. Overall, it reduces the need for additional inputs or outputs while improving upon a device’s functionality.

These functional blocks convert data between serial data and parallel interfaces in either direction. The primary utilization of SerDes is to facilitate data transmission over a single-line or a differential pair to mitigate the number of input pins, output pins, and interconnects.

In summary, we utilize SerDes for the conversion of incoming parallel data into serial data. We transmit this input data via a physical channel like fiber, copper-twisted pair, or even a backplane. The data that we receive is serial data via our physical channels, and the receiver converts this data back into parallel data. The overall process affords designers the ability to increase data transmission speed between two points within a system without the need for additional pins on a component.

The Functional Architecture of SerDes

The basic functional architecture and signaling requirements at each end of SerDes (Tx and Rx) are typically unidirectional. However, in today’s high-speed data applications, you will also encounter bidirectional single links or full-duplex. We usually find these full-duplex links in COTS (commercial off-the-shelf) optical transceivers.

Depending on whether the chip is input, output, or pin-limited, SerDes can increase die cost or decrease die cost in comparison to utilizing a parallel interface. However, at the PCB level or package level, SerDes technology affords the reduction of both traces and pin counts. This typically results in a reduction of package size as well as increased cost-effectiveness in PCB designs and packages.

There is another overall purpose for the utilization of this technology. SerDes affords the transmission of a substantial amount of data (point-to-point) while also reducing the cost, complexity, board-space requirements, and power linked to parallel data bus implementation.

How SerDes Use Affects Functionality

As we have discussed, SerDes is a device composed of functional blocks. The technology compresses wider bit-width, single-ended signal buses into a few, or even one, differential signals. These compressed differential signals typically switch at a much higher frequency rate than the wider single-ended data bus. As you might imagine, the utilization of SerDes technology becomes particularly beneficial at higher frequency rates, for example, parallel data buses of 500 MHz or higher (1000 Mbps).

The reason for this is simple; at higher-frequency rates, the issues related to parallel buses increase. The faster-switching parallel bus is subject to increased routing difficulties and increased power usage. Also, it is worth noting that these increased routing difficulties directly correlate to the reduction in timing tolerances.

Although there are design and verification complexities associated with SerDes technology usage, it is still an indispensable part of SoC (System on a Chip) blocks. Presently, with the availability of SerDes IP blocks, we also see increased mitigation in terms of risks, time to market issues, and overall cost.

Why Use SerDes?

The most apparent advantage of utilizing SerDes technology is the reduction in cable or channel count and pin count. Initially, the technology provided a means to transmit bytes of data across fiber or coax cable. However, in today’s applications, this translates into the ability to transmit bytes of data via a pair of differential signal pins instead of 8, 16, or more data pins and a clock pin.

This manner of serialization directly correlates to decreased cost due to denser PCBs and smaller packages. Overall, the specifics of these advantages are contingent on the cost of the package, die, PCB, and other factors, including PCB congestion.

Another advantage of using SerDes technology is the ability to transmit long distances across both PCBs and backplanes. This ability afforded new design and application considerations for PCBs. The use of SerDes undoubtedly afforded greater functionality and broadened various device applications as a whole.

If we zoom out chronologically, we can view how over the past two decades, SerDes technology continued to evolve and migrate. Its bounds extend far beyond that of optical or networking circuits. In today’s electronic landscape, we experience SerDes in virtually every application from laptops, televisions, to yes, even our smartphones. We also see the technology utilized in data centers as well.

With the onset of 5G and its theoretical speeds of 10Gbps, the need for SerDes technology will only increase.

Microcontrollers with embedded SerDes for IoT Applications

Microcontrollers with embedded SerDes for IoT Applications

SerDes design strategies can be implemented with plenty of Cadence’s design and analysis tools. To get you started, Allegro can work through the layout and circuit components of any PCB design as well as work together toward the production and finalization of these designs. 

If you’re looking to learn more about how Cadence has the solution for you, talk to us and our team of experts.

 

About the Author

Cadence PCB solutions is a complete front to back design tool to enable fast and efficient product creation. Cadence enables users accurately shorten design cycles to hand off to manufacturing through modern, IPC-2581 industry standard.

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